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Preliminary GS88418/36B-200/180/166/150/133 119-Bump BGA Commercial Temp Industrial Temp
Features
* FT pin for user-configurable flow through or pipelined operation * Single/Dual Cycle Deselect Selectable * ZQ mode pin for user-selectable high/low output drive strength * 3.3 V +10%/-5% core power supply * 2.5 V or 3.3 V I/O supply * LBO pin for Linear or Interleaved Burst mode * Internal input resistors on mode pins allow floating mode pins * Default to SCD x18/x36 Interleaved Pipeline mode * Byte Write (BW) and/or Global Write (GW) operation * Common data inputs and data outputs * Clock Control, registered, address, data, and control * Internal self-timed write cycle * Automatic power-down for portable applications * 119-bump BGA package
512K x 18, 256K x 36 8Mb S/DCD Sync Burst SRAMs
Flow Through/Pipeline Reads
200 MHz-133 MHz 3.3 V VDD 3.3 V and 2.5 V I/O
(LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance. The function of the Data Output register can be controlled by the user via the FT mode bump (Bump 5R). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the risingedge-triggered Data Output Register.
SCD and DCD Pipelined Reads
The GS88436B is a SCD (Single Cycle Deselect) and DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD SRAMs pipeline disable commands to the same degree as read commands. SCD SRAMs pipeline deselect commands one stage less than read commands. SCD RAMs begin turning off their outputs immediately after the deselect command has been captured in the input registers. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock. The user may configure this SRAM for either mode of operation using the SCD mode input on Bump 4L.
Pipeline 3-1-1-1 Flow Through 2-1-1-1
tCycle tKQ IDD tKQ tCycle IDD
-200 5.0 3.0 450 7.5 10 270
-180 5. 5 3.2 410 8 10 270
-166 6.0 3.5 380 8.5 10 250
-150 6.7 3.8 350 9.0 10 240
-133 7.5 4.0 340 9.5 10 220
Unit ns ns mA ns ns mA
Byte Write and Global Write
Byte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.
Functional Description
Applications
The GS88418/36B is a 9,437,184-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAM applications, ranging from DSP main store to networking chip set support.
FLXDriveTM
The ZQ pin allows selection between high drive strength (ZQ low) for multi-drop bus applications and normal drive strength (ZQ floating or high) point-to-point applications. See the Output Driver Characteristics chart for details.
Controls
Addresses, data I/Os, chip enables (E1, in x18 version, E1 and E2 in x36 version), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power-down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear or interleave order with the Linear Burst Order Rev: 1.05 10/2001 1/25
Sleep Mode
Low power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.
Core and Interface Voltages
The GS884B operates on a 3.3 V power supply and all inputs/ outputs are 3.3 V- and 2.5 V-compatible. Separate output power (VDDQ) pins are used to decouple output noise from the internal circuit.
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 GS88436 Pad Out
119-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQC4 DQC3 VDDQ DQC2 DQC1 VDDQ DQD1 DQD2 VDDQ DQD3 DQD4 NC NC VDDQ
2
A6 E2 A5 DQPC9 DQC8 DQC7 DQC6 DQC5 VDD DQD5 DQD6 DQD7 DQD8 DQPD9 A2 NC NC
3
A7 A4 A3 VSS VSS VSS BC VSS NC VSS BD VSS VSS VSS LBO A10 NC
4
ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD A11 NC
5
A8 A15 A14 VSS VSS VSS BB VSS NC VSS BA VSS VSS VSS FT A12 NC
6
A9 A17 A16 DQPB9 DQB8 DQB7 DQB6 DQB5 VDD DQA5 DQA6 DQA7 DQA8 DQPA9 A13 NC NC
7
VDDQ NC NC DQB4 DQB3 VDDQ DQB2 DQB1 VDDQ DQA1 DQA2 VDDQ DQA3 DQA4 NC ZZ VDDQ
Rev: 1.05 10/2001
2/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 GS88418 Pad Out
119-Bump BGA--Top View
1 A B C D E F G H J K L M N P R T U
VDDQ NC NC DQB1 NC VDDQ NC DQB4 VDDQ NC DQB6 VDDQ DQB8 NC NC NC VDDQ
2
A6 NC A5 NC DQB2 NC DQB3 NC VDD DQB5 NC DQB7 NC DQB9 A2 A10 NC
3
A7 A4 A3 VSS VSS VSS BB VSS NC VSS NC VSS VSS VSS LBO A11 NC
4
ADSP ADSC VDD ZQ E1 G ADV GW VDD CK SCD BW A1 A0 VDD NC NC
5
A8 A15 A14 VSS VSS VSS NC VSS NC VSS BA VSS VSS VSS FT A12 NC
6
A9 A17 A16 DQA9 NC DQA7 NC DQA5 VDD NC DQA3 NC DQA2 NC A13 A18 NC
7
VDDQ NC NC NC DQA8 VDDQ DQA6 NC VDDQ DQA4 NC VDDQ NC DQA1 NC ZZ VDDQ
Rev: 1.05 10/2001
3/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 GS88418/36 BGA Pin Description
Pin Location
P4, N4 A2, A3, A5, A6, B3, B5, C2, C3, C5, C6, G4, R2, R6, T3, T5 T4 T2, T6 T2, T6 K7, L7, N7, P7, K6, L6, M6, N6, P6 H7, G7, E7, D7, H6, G6, F6, E6, D6 H1, G1, E1, D1, H2, G2, F2, E2, D2 K1, L1, N1, P1, K2, L2, M2, N2, P2 L5, G5, G3, L3 P7, N6, L6, K7, H6, G7, F6, E7, D6 D1, E2, G2, H1, K2, L1, M2, N1, P2 L5, G3 P6, N7, M6, L7, K6, H7, G6, E6, D7, D2, E1, F2, G1, H2, K1, L2, N2, P1, G5, L3, T4 K4 E4 B2 F4 T7 R5 R3 L4 D4 B1, C1, R1, T1, L4, B7, C7, U6, R7, J3,J5, U2, U3, U4, U5 J2, C4, J4, R4, J6 D3, E3, F3, H3, K3, M3, N3, P3, D5, E5, F5, H5, K5, M5, N5, P5 A1, F1, J1, M1, U1, A7, F7, J7, M7, U7
Symbol
A0, A1 An An NC An DQA1-DQPA9 DQB1-DQPB9 DQC1-DQPC9 DQD1-DQPD9 BA, BB, BC, BD DQA1-DQA9 DQB1-DQB9 BA, BB NC CK E1 E2 G ZZ FT LBO SCD ZQ NC VDD VSS VDDQ
Type
I I I -- I I/O I I/O I -- I I I I I I I I I -- I I I
Description
Address field LSBs and Address Counter Preset Inputs Address Inputs Address Inputs (x36 Version) No Connect (x36 Version) Address Inputs (x18 Version) Data Input and Output pins (x36 Version) Byte Write Enable for DQA, DQB, DQC, DQD I/Os; active low ( x36 Version) Data Input and Output pins (x18 Version) Byte Write Enable for DQA, DQB Data I/Os; active low ( x18 Version) No Connect (x18 Version) Clock Input Signal; active high Chip Enable; active low Chip Enable; active high Output Enable; active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Single Cycle Deselect/Dual Cycle Deselect Mode Control FLXDrive Output Impedance Control (Low = Low Impedance [High Drive], High = High Impedance [Low Drive]) No Connect Core power supply I/O and Core Ground Output driver power supply
BPR2000.002.14
Rev: 1.05 10/2001
4/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
GS88418/36 Block Diagram
Register
A0-An
D
Q A0 D0 A1 D1 Q1 Counter Load A Q0 A0 A1
LBO ADV CK ADSC ADSP GW BW BA
Register
Memory Array
Q D Q D
Register
D BB
Q
18 4
18
Register
D BC
Q Q
Register
D
Register
Q
Register
D
D BD
Q
Register
D
Q
Register
E1
D
Q
Register
D FT G Power Down Control
Q
ZZ
DCD=0 SCD=1
DQx0-DQx9
Note: Only x18 version shown for simplicity.
Rev: 1.05 10/2001
5/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
Mode Pin Functions Mode Name
Burst Order Control Output Register Control Power Down Control Single/Dual Cycle Deselect Control FLXDrive Output Impedance Control
Pin Name
LBO FT ZZ SCD ZQ
State
L H or NC L H or NC L or NC H L H or NC L H
Function
Linear Burst Interleaved Burst Flow Through Pipeline Active Standby, IDD = ISB Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance)
Note: There are pull-up devices on the LBO, ZQ, SCD, and FT pins and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above table.
Enable / Disable Parity I/O Pins
This SRAM allows the user to configure the device to operate in Parity I/O active (x18 or x36) or in Parity I/O inactive (x16 or x32) mode. Holding the PE bump low or letting it float will activate the 9th I/O on each byte of the RAM. Tying PE high deactivates the 9th I/O of each byte, although the bit in each byte of the memory array remains active to store and recall parity bits generated and read into the ByteSafe parity circuits.
Burst Counter Sequences
Linear Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0] 1st address 2nd address 3rd address 4th address 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 1st address 2nd address 3rd address 4th address
Interleaved Burst Sequence
A[1:0] A[1:0] A[1:0] A[1:0] 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
BPR 1999.05.18
Note: The burst counter wraps to initial state on the 5th clock.
Note: The burst counter wraps to initial state on the 5th clock.
Rev: 1.05 10/2001
6/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
Byte Write Truth Table
Function
Read Read Write byte a Write byte b Write byte c Write byte d Write all bytes Write all bytes
GW
H H H H H H H L
BW
H L L L L L L X
BA
X H L H H H L X
BB
X H H L H H L X
BC
X H H H L H L X
BD
X H H H H L L X
Notes
1 1 2, 3 2, 3 2, 3, 4 2, 3, 4 2, 3, 4
Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC, and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes "C" and "D" are only available on the x36 version.
Rev: 1.05 10/2001
7/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
Synchronous Truth Table Operation
Deselect Cycle, Power Down Deselect Cycle, Power Down Deselect Cycle, Power Down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst
Address Used
None None None External External External Next Next Next Next Current Current Current Current
State Diagram Key5
X X X R R W CR CR CW CW
E1
H L L L L L X H X H X H X H
E22
(x36only)
ADSP ADSC
X L H L H H H X H X H X H X L X L X L L H H H H H H H H
ADV
X X X X X X L L L L H H H H
W3
X X X X F T F F T T F F T T
DQ4
High-Z High-Z High-Z Q Q D Q Q D D Q Q D D
X F F T T T X X X X X X X X
Notes: 1. X = Don't Care, H = High, L = Low. 2. For x36 Version, E = T (True) if E2 = 1; E = F (False) if E2 = 0. 3. W = T (True) and F (False) is defined in the Byte Write Truth Table preceding. 4. G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shown as "Q" in the Truth Table above). 5. 6. 7. All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplish basic synchronous or synchronous burst operations and may be avoided for simplicity. Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above. Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.
Rev: 1.05 10/2001
8/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Simplified State Diagram
X
Deselect W W Simple Synchronous Operation R R
X CW
First Write
R CR
First Read
X CR
Simple Burst Synchronous Operation
W R X Burst Write CR CW
R
Burst Read
X
CR
Notes: 1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low. 2. The upper portion of the diagram assumes active use of only the Enable (E1 and E2) and Write (BA, BB, BC, BD, BW, and GW) control inputs, and that ADSP is tied high and ADSC is tied low. 3. The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, and assumes ADSP is tied high and ADV is tied low.
Rev: 1.05 10/2001
9/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Simplified State Diagram with G
X
Deselect W W X W CW R R
First Write
R CR
First Read
X CR
CW
W X Burst Write R CR W CW
R X
Burst Read
CW
CR
Notes: 1. The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G. 2. Use of "Dummy Reads" (Read Cycles with G High) may be used to make the transition from read cycles to write cycles without passing through a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles. 3. Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM's drivers off and for incoming data to meet Data Input Set Up Time.
Rev: 1.05 10/2001
10/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
Absolute Maximum Ratings
(All voltages reference to VSS)
Symbol
VDD VDDQ VCK VI/O VIN IIN IOUT PD TSTG TBIAS
Description
Voltage on VDD Pins Voltage in VDDQ Pins Voltage on Clock Input Pin Voltage on I/O Pins Voltage on Other Input Pins Input Current on Any Pin Output Current on Any I/O Pin Package Power Dissipation Storage Temperature Temperature Under Bias
Value
-0.5 to 4.6 -0.5 to VDD -0.5 to 6 -0.5 to VDDQ +0.5 ( 4.6 V max.) -0.5 to VDD +0.5 ( 4.6 V max.) +/-20 +/-20 1.5 -55 to 125 -55 to 125
Unit
V V V V V mA mA W
oC o
C
Note: Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component.
Recommended Operating Conditions Parameter
Supply Voltage I/O Supply Voltage Input High Voltage Input Low Voltage Ambient Temperature (Commercial Range Versions) Ambient Temperature (Industrial Range Versions)
Symbol
VDD VDDQ VIH VIL TA TA
Min.
3.135 2.375 1.7 -0.3 0 -40
Typ.
3.3 2.5 -- -- 25 25
Max.
3.6 VDD VDD +0.3 0.8 70 85
Unit
V V V V C C
Notes
1 2 2 3 3
Notes: 1. Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 2.75 V VDDQ 2.375 V (i.e., 2.5 V I/O) and 3.6 V VDDQ 3.135 V (i.e., 3.3 V I/O), and quoted at whichever condition is worst case. 2. This device features input buffers compatible with both 3.3 V and 2.5 V I/O drivers. 3. Most speed grades and configurations of this device are offered in both Commercial and Industrial Temperature ranges. The part number of Industrial Temperature Range versions end the character "I". Unless otherwise noted, all performance specifications quoted are evaluated for worst case in the temperature range marked on the device. 4. Input Under/overshoot voltage must be -2 V > Vi < VDD +2 V with a pulse width not to exceed 20% tKC.
Rev: 1.05 10/2001
11/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
Undershoot Measurement and Timing
VIH VDD + 2.0 V VSS 50% VSS - 2.0 V 20% tKC VIL 50% VDD
Overshoot Measurement and Timing
20% tKC
Capacitance
(TA = 25oC, f = 1 MHZ, VDD = 3.3 V)
Parameter
Input Capacitance Input/Output Capacitance Note: These parameters are sample tested.
Symbol
CIN CI/O
Test conditions
VIN = 0 V VOUT = 0 V
Typ.
4 6
Max.
5 7
Unit
pF pF
Package Thermal Characteristics Rating
Junction to Ambient (at 200 lfm) Junction to Ambient (at 200 lfm) Junction to Case (TOP)
Layer Board
single four --
Symbol
RJA RJA RJC
Max
40 24 9
Unit
C/W C/W C/W
Notes
1,2 1,2 3
Notes: 1. Junction temperature is a function of SRAM power dissipation, package thermal resistance, mounting board temperature, ambient. Temperature air flow, board density, and PCB thermal resistance. 2. SCMI G-38-87 3. Average thermal resistance between die and top surface, MIL SPEC-883, Method 1012.1
Rev: 1.05 10/2001
12/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133
AC Test Conditions Parameter
Input high level Input low level Input slew rate Input reference level Output reference level Output load
Conditions
2.3 V 0.2 V 1 V/ns 1.25 V 1.25 V Fig. 1& 2
Notes: 1. Include scope and jig capacitance. 2. Test conditions as specified with output loading as shown in Fig. 1 unless otherwise noted. 3. Output Load 2 for tLZ, tHZ, tOLZ and tOHZ 4. Device is deselected as defined by the Truth Table. Output Load 1 DQ 50 VT = 1.25 V
* Distributed Test Jig Capacitance
Output Load 2 2.5 V 30pF* DQ 5pF* 225 225
DC Electrical Characteristics Parameter
Input Leakage Current (except mode pins) ZZ Input Current Mode Pin Input Current Output Leakage Current Output High Voltage Output High Voltage Output Low Voltage
Symbol
IIL IINZZ IINM IOL VOH VOH VOL
Test Conditions
VIN = 0 to VDD VDD VIN VIH 0 V VIN VIH VDD VIN VIL 0 V VIN VIL Output Disable, VOUT = 0 to VDD IOH = -4 mA, VDDQ = 2.375 V IOH = -4 mA, VDDQ = 3.135 V IOL = 4 mA
Min
-1 uA -1 uA -1 uA -300 uA -1 uA -1 uA 1.7 V 2.4 V --
Max
1 uA 1 uA 300 uA 1 uA 1 uA 1 uA -- -- 0.4 V
Rev: 1.05 10/2001
13/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Operating Currents
-200 Parameter Test Conditions Device Selected; All other inputs VIH or VIL Output open Symbol IDD Pipeline IDD Flow Through ISB Pipeline ISB Flow Through IDD Pipeline IDD Flow Through 0 to 70C 450 270 40 40 120 90 -40 to 85C 470 290 60 60 140 110 -180 -166 -150 -133 Unit 0 -40 0 -40 0 -40 0 -40 to to to to to to to to 70C 85C 70C 85C 70C 85C 70C 85C 410 270 40 40 110 80 430 290 60 60 130 100 380 250 40 40 100 80 400 270 60 60 120 100 350 240 40 40 100 70 370 250 60 60 120 90 340 220 40 40 90 70 360 240 60 60 110 90
Operating Current
mA mA mA mA mA mA
Standby Current
ZZ VDD - 0.2 V
Deselect Current
Device Deselected; All other inputs VIH or VIL
Rev: 1.05 10/2001
14/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 AC Electrical Characteristics
Parameter Clock Cycle Time Pipeline Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock Cycle Time Flow Through Clock to Output Valid Clock to Output Invalid Clock to Output in Low-Z Clock HIGH Time Clock LOW Time Clock to Output in High-Z G to Output Valid G to output in Low-Z G to output in High-Z Setup time Hold time ZZ setup time ZZ hold time ZZ recovery Symbol tKC tKQ tKQX tLZ
1
-200 Min 5.0 -- 1.5 1.5 10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20 Max -- 3.0 -- -- -- 7.5 -- -- -- -- 3.0 3.2 -- 3.0 -- -- -- -- -- Min 5.5 -- 1.5 1.5
-180 Max -- 3.2 -- -- -- 8.0 -- -- -- -- 3.2 3.2 -- 3.2 -- -- -- -- -- Min 6.0 -- 1.5 1.5
-166 Max -- 3.5 -- -- -- 8.5 -- -- -- -- 3.5 3.5 -- 3.5 -- -- -- -- -- Min 6.7 -- 1.5 1.5
-150 Max -- 3.8 -- -- -- 9.0 -- -- -- -- 3.8 3.8 -- 3.8 -- -- -- -- -- Min 7.5 -- 1.5 1.5
-133 Max -- 4.0 -- -- -- 9.5 -- -- -- -- 4.0 4.0 -- 4.0 -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tKC tKQ tKQX tLZ1 tKH tKL tHZ1 tOE tOLZ1 tOHZ1 tS tH tZZS2 tZZH2 tZZR
10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
10.0 -- 3.0 3.0 1.3 1.5 1.5 -- 0 -- 1.5 0.5 5 1 20
Notes: 1. These parameters are sampled and are not 100% tested. 2. ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold times as specified above.
Rev: 1.05 10/2001
15/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Write Cycle Timing
Single Write
Burst Write
Write
Deselected
CK
tS tH
tKH tKL
tKC
ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated write
ADSC
tS tH
ADV
tS tH ADV must be inactive for ADSP Write
WR2 WR3
A0-An
WR1
tS tH
GW
tS tH
BW
tS tH
BA-BD
tS tH
WR1 WR1
WR2
WR3 WR3
E1 masks ADSP
E1
tS tH Deselected with E2
E2*
E2 only sampled with ADSP or ADSC
G
tS tH Write specified byte for 2A and all bytes for 2B, 2C& 2D
D2A D2B D2C D2D D3A
DQA-DQD
Hi-Z
D1A
* Only in 88436B
Rev: 1.05 10/2001
16/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Flow Through Read Cycle Timing
Single Read tKL
Burst Read
CK
tS tH tKH tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC
tS tH Suspend Burst Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW BA-BD
tS tH E1 masks ADSP
E1
tS tH E2 only sampled with ADSP or ADSC Deselected with E2
E2*
tOE tOHZ
G
tOLZ tKQX Q1A tLZ tHZ tKQ Q2A Q2B Q2c Q2D Q3A tKQX
DQA-DQD
Hi-Z
Rev: 1.05 10/2001
17/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Flow Through Read-Write Cycle Timing
Single Read Single Write
Burst Read
CK
tS tH tKH tKL tKC ADSP is blocked by E inactive
ADSP
tS tH ADSC initiated read
ADSC ADV
tS tH
tS tH
A0-An
RD1
WR1
RD2
tS
tH
GW
tS tH
BW
tS tH
BA-BD
tS tH
WR1
E1 masks ADSP
E1
tS tH E2 only sampled with ADSP and ADSC
E2*
tOE tOHZ
G
tKQ tS Q1A tH Q2A Q2B Q2c Q2D Q2A
DQA-DQD
Hi-Z
D1A
Burst wrap around to it's initial state
* Only in 88436B
Rev: 1.05 10/2001
18/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Pipelined SCD Read Cycle Timing
Single Read Burst Read tKH tKL tKC tS tH ADSC initiated read ADSP is blocked by E inactive
CK
tS tH
ADSP ADSC
tS tH
Suspend Burst
ADV
tS tH
A0-An
RD1 tS
RD2
RD3 tH
GW
tS tH
BW
BWA-BWD
tS tH E1 masks ADSP
E1
tS tH E2 only sampled with ADSP or ADSC Deselected with E2
E2*
tOE
G DQA-DQD
Hi-Z tOLZ Q1A tLZ
tOHZ tKQX Q2A Q2B Q2c Q2D
tKQX Q3A tHZ
tKQ * Only in 88436B
Rev: 1.05 10/2001
19/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Pipelined DCD Read-Write Cycle Timing
Single Write Single Read tKL Burst Read
CK
tS tH tKH tKC tS tH ADSP is blocked by E1 inactive
ADSP
ADSC initiated read
ADSC
tS tH
ADV
tS tH
A0-An
RD1
WR1
RD2
tS tH
GW
tS tH tH tS
BW BA-BD
tS tH
WR1
E1 masks ADSP
E1
tS tH E2 only sampled with ADSP and ADSC
E2*
tOE tOHZ
G DQA-DQD
Hi-Z tKQ Q1A tS tH
D1a
Q2A
Q2B
Q2c
Q2D
* Only in 88436B
Rev: 1.05 10/2001
20/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Sleep Mode Timing Diagram
CK
tS tH tKC tKH tKL
ADSP ADSC
tZZS
~ ~~~~ ~ ~~~~ ~
tZZH
tZZR
ZZ
Snooze
Application Tips
Single and Dual Cycle Deselect
SCD devices force the use of "dummy read cycles" (read cycles that are launched normally, but that are ended with the output drivers inactive) in a fully synchronous environment. Dummy read cycles waste performance, but their use usually assures there will be no bus contention in transitions from reads to writes or between banks of RAMs. DCD SRAMs do not waste bandwidth on dummy cycles and are logically simpler to manage in a multiple bank application (wait states need not be inserted at bank address boundary crossings), but greater care must be exercised to avoid excessive bus contention.
Rev: 1.05 10/2001
21/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 FLXDrive Output Driver Characteristics
120.0
100.0 Pull Down Drivers 80.0
60.0
40.0
20.0
VDD I Out
I Out (mA)
0.0
VOut VSS
-20.0
-40.0
-60.0 Pull Up Drivers -80.0
-100.0
-120.0
-140.0 -0.5 0 0.5 1 1.5 2 2.5 3 3.5 4 V Out (Pull Down) VDDQ - V Out (Pull Up) 3.1V PD HD 3.6V PD LD 3.6V PU LD 3.1V PU HD
3.6V PD HD 3.1V PU LD
3.3V PD HD 3.3V PU LD
3.3V PD LD 3.3V PU HD
3.1V PD LD 3.6V PU HD
Rev: 1.05 10/2001
22/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Package Dimensions--119-Pin BGA
Pin 1 Corner
A
7654321
G
P
B
S
D
A B C D E F G H J K L M N P R T U
N
Top View
R Bottom View
Package Dimensions--119-Pin BGA
T
Symbol
A B C D E F G
Description
Width Length Package Height (including ball) Ball Size Ball Height Package Height (excluding balls) Width between Balls Package Height above board Cut-out Package Width Foot Length Width of package between balls Length of package between balls Variance of Ball Height
Min. Nom. Max
13.8 21.8 0.60 0.50 0.75 0.60 1.46 1.27 0.80 0.90 12.00 19.50 7.62 20.32 0.15 1.00 14.0 22.0 14.2 22.2 2.40 0.90 0.70 1.70
K
K N P
F
E
C
R S T
Side View
Unit: mm
Rev: 1.05 10/2001
23/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Ordering Information for GSI Synchronous Burst RAMs
Org
512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 256K x 36 256K x 36 256K x 36 256K x 36 256K x 36 512K x 18 512K x 18 512K x 18 512K x 18 512K x 18 512K x 36 512K x 36 256K x 36 256K x 36 256K x 36
Part Number1
GS88418B-200 GS88418B-180 GS88418B-166 GS88418B-150 GS88418B-133 GS88436B-200 GS88436B-180 GS88436B-166 GS88436B-150 GS88436B-133 GS88418B-200I GS88418B-180I GS88418B-166I GS88418B-150I GS88418B-133I GS88418B-200I GS88418B-180I GS88436B-166I GS88436B-150I GS88436B-133I
Type
S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through S/DCD Pipeline/Flow Through
Package
BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA BGA
Speed2 (MHz/ns)
200/7.5 180/8 166/8.5 150/9 133/9.5 200/7.5 180/8 166/8.5 150/9 133/9.5 200/7.5 180/8 166/8.5 150/9 133/9.5 200/7.5 180/8 166/8.5 150/9 133/9.5
TA3
C C C C C C C C C C I I I I I I I I I I
Status
Not Available
Not Available
Notes: 1. Customers requiring delivery in Tape and Reel should add the character "T" to the end of the part number. Example: GS88418BT. 2. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user. 3. TA = C = Commercial Temperature Range. TA = I = Industrial Temperature Range. 4. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings.
Rev: 1.05 10/2001
24/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Preliminary GS88418/36B-200/180/166/150/133 Revision History
DS/DateRev. Code: Old;
New GS8841836B Rev 1.00 88418_r1; 88418_r1_01 88418_r1_01; 88418_r1_02 88418_r1_02; 88418_r1_03
Types of Changes Page;Revisions;Reason Format or Content
First Release Content Format Content * * Updated BGA pinout to meet JEDEC standards * Updated format to comply with Technical Publications standards * Updated Capitance table--removed Input row and changed Output row to I/O * Updated speed bin table on page 1 (Added 150 MHz and 133 MHz) * Updated pinouts on pages 2 & 3 (U2-U5 should all be NC) * Removed PE, DP, and QE from Pin Description table on page 4; added R7, J3, J5, U2, U3, U4, U5 to NC row * Added 150 MHz and 133 MHz to Operating Currents table on page 14 * Added 150 MHz and 133 MHz to Electrical Characteristics table on page 15 * Deleted BSR table on page 22 * Added references to 150 MHz and 133 MHz speed bins to headers and ordering information table
88418_r1_03; 88418_r1_04
Content
88418_r1_04; 88418_r1_05
Content
Rev: 1.05 10/2001
25/25
(c) 2000, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

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